One type of prior non-volatile integrated circuit memory is the erasable programmable read-only memory ("EPROM"). EPROMs frequently use memory cells that have electrically isolated gates (floating gates). A FAMOS (Floating gate Avalanche injection Metal Oxide Semiconductor) device is a typical example of an EPROM memory cell. Information is stored in the memory cells in the form of charge on the floating gates. The EPROM is programmed by placing a charge on the floating gates. The EPROM can be programmed by a user, and once programmed, the EPROM retains its data until erased. Other memory devices such as Flash EEPROMs (Electrically Erasable Programmable Read Only Memory) are also user programmable. Flash EEPROMs are also programmed by electrically injecting a charge onto the floating gates.
The EPROM comprises memory cells logically organized by rows and columns. Typically, the rows represent word lines and the columns represent bit lines. By selecting the appropriate word line and bit line, each individual cell may be programmed or read. During the programming operation a given memory cell or cells are selected for programming, then a voltage is applied to the control gate of each memory device (e.g. a FAMOS device). A programming voltage is applied to the bit line of each selected memory cell. The programming voltage generates a programming current flowing through the selected bit line, thus programming the memory cell or cells. Due to physical and functional limitations of the memory, the programming current in each bit line must be controlled within certain operating parameters. These physical and functional limitations define a "box" within which the current through the memory cell and the voltage across the source/drain current path of the memory cell (current-voltage characteristic curve) must remain in order to ensure proper programming of the memory cells.
Prior art memories achieved this by incorporating a linear current limiting device in each bit line or for a group of bit lines. The voltage drop across a linear current limiting device is directly proportional to the current through the device. An example of a linear current limiting device would be a resistor. The current-voltage characteristic utilizing a resistor would essentially be a line. The slope of the current-voltage characteristic could be varied by selecting resistors with different values. This linear current-voltage characteristic was often referred to as a "load-line", and this term is often used even when the current-voltage characteristic is not linear. It is used as a general term for the current-voltage characteristic of EPROM programming circuits.
One disadvantage of this prior art memory is that the memory cell could only be operated over a narrow voltage or narrow current range due to the linear nature of the current-voltage characteristic.
Another disadvantage of this prior art memory is that the current-voltage characteristic would shift depending upon how many other memory cells were being programmed. Thus although the slope of the characteristic could be varied, the choices were limited due to having to account for this shifting. Connecting a group of bit lines to draw current through the resistor causes the current through the bit lines to drop when several bit lines are being used to program memory devices. Compensating for this by decreasing the resistor value will cause the current supplied to a single bit line to increase dramatically when no other bit lines are being programmed.
Improved prior art memories substituted a non-linear current limiting device so that the bit lines could be subjected to a greater range of voltages and yet the memory cells would still be operating within desired operational parameters. The current through a non-linear current limiting device is not directly proportional to a voltage across the device.
One example of a current limiting device having a non-linear current-voltage characteristic is a metal oxide semiconductor field effect transistor (MOSFET). A MOSFET has a drain terminal, a source terminal and a gate terminal. When a MOSFET is operating in the linear mode the drain to source current I.sub.DS is essentially directly proportional to the voltage V.sub.DS measured between the drain and the source terminals. When a MOSFET is operating in the saturation mode, the current I.sub.DS is substantially independent of the voltage V.sub.DS. Whether the MOSFET is operating in the linear or saturation mode is controlled by the voltage applied between the gate and source terminals (V.sub.GS). For an n-channel MOSFET, when V.sub.DS &gt;V.sub.GS -V.sub.t the transistor is operating in the saturation mode. For an n-channel MOSFET, when V.sub.DS &lt;V.sub.GS -V.sub.t the transistor is operating in the linear mode. The voltage V.sub.t is often called the threshold voltage.
One disadvantage of this prior art memory is that the current utilized by a given bit line during a programming operation depends on how many other memory cells are being simultaneously programmed. This means that the bit lines must be insensitive to a current which varies a great deal, depending upon how many other cells are being simultaneously programmed. Furthermore, complicated feedback circuits designed to regulate the current in each bit line are undesirable due to the amount of space required for implementation on the integrated circuit containing the memory.
In addition, the memory designer was typically forced to give up desired functionality such as programming speed because of physical limitations such as substrate current. As transistor technologies advance toward smaller dimensions and thinner oxides, the constraints set by programming speed, maximum bit line voltage, and maximum current per bit have become more restrictive, requiring programming load lines that are well regulated over a range of process, voltage, and numbers of bit lines being programmed.